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XiVO Project Blog

XiVO Open minded telecom system. The blog of the XiVO projects.

XiVO IOH first CPU prototype board fully working - part1

Dear followers of our XiVO IPBX OpenHardware project, we are happy to announce that our first version of our prototype for the CPU board (PCB prototyping the CPU and the different interfaces connected to the CPU) is now fully working and we have a full Linux system running on it to start stress-testing our platform (tests of currents and temperature in a full stress mode). We are now getting closer and closer to publish a fully-open design of an IPBX running Linux/Asterisk/XiVO in OpenHardware.

First we had our PCB pick-and-placed in our PCB factory (mainly on a Fuji machine) and you can see below a screenshot from the precision placement camera on the machine

XIOH_CPU_Factory_Cabling_Screenshot

The main concerns of a PCB design when one wants to first test the just "pick-and-placed" board is to follow different steps to prevent undetection of hardware errors of design. These steps are usually (at least, the ones we followed) the following :

  • Smoketest : of the powersupply block doing the different voltages level of the board (crucial for a SoC like the one we are using) by using different DC external powersuplies for the different ATX voltage levels (+12V, -12V, +5V, +5VSBY, +3V3) and limiting the current following the Intel EP80579 datasheet. This test was positive on each of the voltage level and confirming that our power-supply is functionnal in terms of voltage level and current limitations
  • Bringup : booting the board with a correct DDR2 DIMM (1Go) and flashing our version of coreboot build on our 2Mo SPI-flash using a dediprog SF100 SPI programer
  • Connecting the SATA HDD w/ a fully configured Linux kernel and trying to jump from the functionnal coreboot to grub then Linux decompression of the image

Please find below, a picture of the lab deployment of the board powered by external power-supplies and connected to a bus-pirate for the flashing of our bootloader through SPI connexions.

XIOH_CPU_P4_test_1

Once this smoke-test and bring-up test were fully positive and allowing us to move to next step with some stress-tests :

  • Temperature#1 : Running a memtest86+ on the DDR2 and testing the temperature of the CPU package w/ a temperature sensor
  • Temperateur#2 : Running an Intel utility for our SoC (pushing the CPU usage to 100% and memory to 50%) and measuring the temperature
  • Temperature#3 : Putting one of our board into a test metallic case and connecting the board w/ 3 parallel GbE interfaces fully loaded w/ iperf at 1Gbps and measuring the temperature in the case after several hours
  • Bitrate : Iperf'ing the 3xGbE interfaces and measuring the load of the CPU and the transfer bitrates

Please find below, a picture of our lab w/ 2 XIOH CPU boards running our test-program and 3xGbE interfaces connected together one-by-one

XIOH_CPU_P4_test_2

We will update our different tests on the CPU boards and keep you update on the follow-ups of our design steps.

Xavier Carcelle.

OpenHardware landscape Q4 2011

The OpenHardware community is expanding more and more these past months and here a short landscape view of the community nowadays :

  • OpenHardware large board projects

PandaBoard : http://pandaboard.org/sites/default/files/board_reference/EA1/720-2152-001_EA1_BRD.zip
Chumby : http://files.chumby.com/bunnie/chumbyone_hw/chumbyone_gerbers.zip
MilkyMist : http://en.qi-hardware.com/wiki/Milkymist_One_RC1_PCB_Specification
Tormenta v2 PCI card : http://www.zapatatelephony.org/t2/T2B2Gerber.zip

  • OpenHardware smaller board projects

DIY boards : http://tuxgraphics.org/electronics/

  • Open "specifications" Hardware products

Elphel camera : http://www.elphel.com/importwiki?title=353_in_a_nutshell

  • Blogs/Events/Journals

OpenHardwareJournal : http://openhardware.org/journal/2011/11/index.html
Hack-a-day : http://hackaday.com

  • Events/Conferences/Workshops

OpenHardwareSummit : http://www.openhardwaresummit.org/
OpenHardwareWorkshop : http://www.ohwr.org/projects/ohr-meta/wiki/OHWorkshop
OpenSourceHardware2011 (Madrid) : http://oshwcon.org/

  • Licences

OHANDA : http://ohanda.org
CERN : http://www.ohwr.org/projects/cernohl/wiki/CernOhlProjects
OpenSourceHardwareDefintion : http://freedomdefined.org/OSHW

PCB prototypes and flash SPI testing

On the XiVO Open Hardware side, we have been very busy lately writing various bits of low level software, preparing the production of the first prototypes, validating some hardware subsystems and doing all sort of hardware + low level software debugging.

We are starting again to have things interesting to show, with some cute photos.

PCB prototypes

We recently received our first PCB prototypes for our motherboard:

XIOH motherboard prototype

To prepare for testing the first assembled prototypes, we wanted to somehow test the communication between the EP80579 and the SPI flash. For now we have a 74LVC125A buffer between the two chips in order to isolate the flash from the SoC, and we wanted to validate this design.

We previously did a small model of the flash subsystem, A few days ago I heavily hacked it to make it work. (Well some of the modifications were probably not really necessary, but now we have a perfect signal quality :)

Heavily hacked flash prototype board

The next step was to do the same test, this time using one of our spare naked PCBs dedicated to that kind of testing. We first soldered the flash and the buffer, then we strapped a HE10 ISP header to replace the EP80579 SPI drivers by a flash programmer (this is obviously not a perfect replacement, but we can't do much better...)

Here is a photo of the header being soldered:

Soldering an SPI header at SoC position

Here is the soldered result, connected to the programmer:

Testing flash communication

And here is the result:

SPI flash communication test results

So we are now hopeful that at least the SPI flash communication will work on our assembled board \o/

Sourcing the components and scripting the components parts e-shops (digikey, ...)

XiVO IOH BoM Screenshot

Once one approaches the final routing of a PCB for a hardware project, he should think about starting the sourcing of the components (at least the major part that is definitive on the design before the final tests/debugs/redesign without any change of the block diagram) in order to plan the right time in advance the arrival of the components to cable the PCB in the factory. This approach lead to find out which part will take the longest time to be arriving in the complete BoM and that could delay the cabling of the PCB (usually Tantalum Capacitor or specific suppliers of parts). We are now working on the sourcing of each of the component from the major part e-shop as well as the major parts supplier. The project planning can be drastically impacted by some difficulties on the sourcing and it is always important to forecast the part stock in collaboration w/ the production facilities.

Continue reading...

Moving forward to the production of the prototypes - FXO/FXS boards

As the XiVO IPBX OpenHardware project moves forward to the production of our first protoboards for our internal tests, we are pleased to give a first display of the PCB board file for the FXO/FXS interfaces on the IPBX that are routed from the XHFC-4SU controller :

XiVO IOH FXOFXSv5 PCB

When one designs a PCB, it's requires to create two files in order to reach the final board ready for production (we will give more posts about the production files needed for the electronic factories receiving them once we reach this level of the project) : the .SCH (Schematics file with all the electrical connexions between the components and the chips on-board) and the .BRD (Board file with the actual real-sized PCB and the components position with all the net connexions). This image displays the .BRD file designed for the FXO/FXS interfaces.

Visiting CologneChip AG : The ISDN Chip company !

We had the pleasure to visit the CologneChip AG engineering team this week in Koln, Germany and exchange on the ISDN markets and chips (and the different market penetration of ISDN, FTTH, DOCSIS, xDSL in Europe countries). ISDN is still strong in Germany w/ 29 Millions subscribers (22M analog subscribers and 6M subscribers w/ DOSCIS and xDSL - sources: Bundesnetzagentur) and still allow over the 144Kbits/s of net data rate, 2 bearer channels (B-channels) w/ 64Kbits/s each which is equivalent to 3.4Khz voice channel at 8 ksamples/second. The XiVO IPBX OpenHardware will propose 4 BRI (also called S0 for point-to-multipoint BRI type) interfaces to allow these data and voice applications.

  • Please find below the Koln cathedral that you can find on the XHFC-4SU chip:

Koln Cathedral

  • The entrance of the CologneChip AG offices below:


cologneChip offices

Participation to IPConvergence 2010 - Feedbacks and pictures

It was a great pleasure to be participating to the IPConvergence telecommunications fair and present the XiVO IPBX OpenHardware project.

  • Please find below our prototype cased in a 1U rack for demonstrations and presentations of the project:

XiVO OIH 0.1 cased in 1U rack

  • Below is a picture of the booth at IPConvergence fair:

IPConvergence XiVO booth

  • Finally, for vintage telephony geeks, the famous french Socotel S63 in orange (XiVO color):

FT Socotel S63 orange 1983

Participation to the OpenHardwareSummit : OHANDA representation and feedbacks

It was a great pleasure to participate to the OpenHardwareSummit2010 in the New York City Museum of Science and representing the OHANDA trademark during the LAW panel. Thanks to Alicia and Ayah to have organized such an event that gives publicity to the OpenHardware movement out-there. I have surely pushed the usage of the world OpenHardware (versus the OpenSource-Hardware term that seems to close to OpenSource software) for the future as the common term for the hardware projects opening their production and design files. The audience was 200 people and mainly north-american and that was a great pleasure to speak and recall the great previous OpenHardware projects launched in Europe since years now (OpenMoko, OpenPCD, Milkymist, OpenPattern...).

The summit was a one-day long session of presentations and panel discussions followed by an exchange about the OpenHardware definition. During the LAW panel discussion, I had the opportunity to present the OHANDA trademark and

Some discussions panels attracted my attention :

* PRODUCTIZING: Scaling/ Manufacturing/ Moving beyond DIY :

OHS2010 - Production panel

This talk was a great opportunity to have the feedbacks of a production facilities (Clint Cooley from Circuit Co) that supports OpenHardware projects in the US and see a great ramp-up of the projects requesting small, medium and large fab of the their PCBs. We can see that some manufacturers will play a great role in this field and some OpenHardware project will be able to mutualize some aspects of the production for bigger PCBs (more layers, 200-500-1000 components-BOM...).

* BUSINESS: Open hardware business models :

OHS2010 - Marketing panel

This talk gives the occasion to hear several business model of OpenHardware companies ("yes" there is a business model for OpenHardware projects up to several 100k units per product a year) w/ the participation of prototyping and products companies such as Chumby (represented by Bunny skype-ing from Singapore). Definitely the opening of the design and production files is giving business opportunities for partners (resellers, hardware-mods, software-hacks, global solutions) rather than opening the pandora box of copies for cheaper was the global conclusion of this panel discussion.

* LAW: Open hardware licenses and norms :

OHS LawPanel 1

This panel discussion was the occasion to have around the table several legal opinions (with lawyers, Peter Brown from the FSF, a hardware hacker) leading to the following topics :

* What is the interest of opening hardware ?
* How to protect a licence/trademark-ed OpenHardware project in case of legal violation from a files point of view ?
* What about the closed documentation of the chips used in an OpenHardware ?
* What about the firmware used in SoC -based OpenHardware projects ?

Perter Brown from FSF was applausing the 4 freedoms of the OHANDA trademark adapting the ones from the FSF licence.

Below I have collected some documentations and informations about the OHS2010 :

Pictures of the OHS 2010

Transcripts of the talks during the summit :

Transcripts of the talks

Audio MP3 archives :

Audio MP3 archives of the OHS

Audio MP3 archives of the LAW panel

XiVO IPBX OpenHardware selected for the innovation trophy

IPConvergence 2010

We are very pleased to announce that the XiVO IPBX OpenHardware product has been selected for the Innovation Trophy at the IPConvergence technology trade in Paris (Oct. 19-20-21 2010) in the category "Best innovative technology for enterprise unified communications" (in French : L’innovation technologique de l’année dans les communications d’entreprise).

IPConvergence Innovation Trophies nomination


We will be presenting the XiVO IPBX OpenHardware during this trade-show using our brand new logo for the project.

Logo XiVO IPBX OpenHardware

KiCad walkthrough - Part 2

The first article of this series was about using the EESchema schematic editor.

This short article will explain how to assign module footprints to schematic components.

Continue reading...

IEEE MAC OUI Bloc registration for the XiVO IPBX OpenHardware - [08-D2-9A]

We are very pleased to update our followers with the different steps of the process of design of our XiVO IPBX OpenHarware. Most of us work since several years in the telecommunication field and have been using extensively MAC Ethernet addresses on numerous networks appliances at the Layer 2.

Since a network appliance has one/several Ethernet interfaces based on a MAC (IEEE 802.3 controller) and PHY (Signaling and physical interface to the Ethernet connector) interfaces, the unique OUI MAC addresses are stored in a non-volatile memory in the Ethernet chip or in a companion memory on-board. These unique IEEE OUI MAC addresses are usually transparent for the hardware designer as they are registered by the MAC/PHY chip manufacturers to IEEE registration office.

In our case, we will have a SoC integrating the IEEE 802.3 MAC controller and storing the 3 Ethernet MAC addresses in a flash memory. Therefore we have been registrating our own IEEE MAC OUI bloc to be used in our different network hardware projects. This IEEE OUI bloc will then be available publicly with the update of Ethernet sniffer/dissectors after August 31st 2010.

This bloc will be 08-D2-9A and the XiVO IPBX OpenHardware will appear as 08-D2-9A-XX-XX-XX on the Ethernet networks.

A search on Proformatique on the IEEE OUI and Company_id search interface help to retrieve the associated informations.

Representing OHANDA at the OpenHardwareSummit (NYC, 23/9/10)

OpenHardwareSummit

OHANDA Logo

We are very pleased to announce that we will be participating to the OpenHardwareSummit [1] in New York (on Sept. 23rd) representing the OHANDA Trademark during a discussion panel called "LAW: Open hardware licenses and norms" . This is a great opportunity for us (OHANDA TM, OpenHardwareInitiative, OpenTechSummit organizers) to present the work done w/ the OHANDA trademark and exchange about the best licenses/trademarks/standards to commonly use during our different OpenHardware projects to reach the same credibility to this community as for the OpenSource community.

The panel will be as followed :

LAW: Open hardware licenses and norms

• Moderator: Dave Mellis, Arduino & MIT Media Lab • Windell Oskay, Evil Mad Scientist • Wendy Seltzer, Harvard University: Berkman Center for Internet & Society • Matt Stack, Liquidware • Michael Weinberg, Public Knowledge • Peter Brown, Freedom Software Foundation • Xavier Carcelle, OHANDA

We will post during the OpenHardwareSummit to blog the outcome of the panel and others discussions there.

Notes

[1] http://www.openhardwaresummit.org/schedule/

KiCad walkthrough - Part 1

We are writing a series of articles using our prototyping work as a pretext of a small walkthrough of the KiCad suite. This article is the first one of the series. It deals with generalities about the suite and the EESchema schematic editor.

Continue reading...

Giving more tools, hints and URLs to the community

In the world of the OpenHardware projects, we do aim at giving to the community more hints about prototyping hardware, understanding (also reversing) existing hardware, hacking (in the sense of modifying and adding more unexpected features) equipments, reusing "old" hardware and sharing production and lab facilities. The last years had seen a number of blogs and URLs in this field such as:

  • Name that ware: The famous blog from BunnyStudios that post regularly a pictures of a PCB where you should discover the name of the original electronic products behind. Bunny is also the hardware developper behind the Chumby.
  • AdaFruit: A blog/portal dedicated to making some hardware devices (usually micro-controllers) and a load of tutorials
  • Sump from Michael Poppitz who developed the hardware for the famous OpenBench LogicSniffer based on a FPGA that allows a very flexible LogicAnalyzer w/ up to 32channels (16 on a H10-2.54mm header and 16 on-pcb) and 200MHz frequence sampling
  • DangerousPrototypes: A portal that proposes a new OpenHardware project everymonth and distributes numerous prototyping hardware and tools including some hints to make your own laser-cut case for your OpenBench logic analyzer or PirateBus analyzer.
  • Hackmii: A hardware hacking blog dedicated mostly to the Wii hacking but with a lots of tutorials and hardware exploits and a link with forum that somehow more difficult to find.

[Prototype] Description of the functionnal buses

As this OpenHardware project moves forward, we are now approaching a complete prototyping of our functionnal blocks and telecommunications interfaces control from the Linux kernel. The main functionnal blocks to be tested and validated are in our architecture based on the following buses:

  • SPI (Serial Peripheral Interface) bus between the CPU and the FXO/FXS chip
  • LEB (Local Expansion Bus) between the CPU and the ISDN chip
  • TDM (Time Division Multiplexing) connecting the CPU, ISDN and FXO/FXS chip together to transmit the digial streams of voice channels
  • GPIO (General Purpose Input Output) for the RST (Reset) signals and IRQ (Interrupts) signals
  • CLK (Clock) signals architecture to be sent to the different chips

Below is a picture of our prototype boards connected together to demonstrate the functionnalities of each blocks for our software development on the Linux kernel modules:

XiVO IPBX Prototype WishBoard-108

We have been using the large prototyping breaboard from Wisher (at farnell.com on: http://fr.farnell.com/jsp/search/productdetail.jsp?SKU=1472854) that is great to split different wires connectivity on the breadboard.

In the next posts, we will describe the results and work done on each buses to achieve the first global tests for voice channel routing with our XiVO IPBX OpenHardware.

The first OpenHardwareSummit and more OpenHardware movements

We see currently a great energy and interest for the OpenHardware movement with different groups or consortiums aiming at creating a common energy in this. The OHANDA Trademark is definitely a great baseline for the upcoming OpenHardware project to have a legal umbrella and present their project files in a central repository where the users/customers of the OHANDA trademark-ed products will be able to find the documents/files need to understand/modify/improve within the respect of this trademark.

This week, 2 more news came out in the OpenHardware movement with:

  • A common definition of the OpenHardware 0.3. [1]. The definition is derived from the Open Source Definition, which was created by Bruce Perens and the Debian developers as the Debian Free Software Guidelines
  • The announcement of the OpenHardwareSummit [2] to be held the September23rd in NYC, US. This event will be supported by Chris Anderson (Wired), Mako Hill (OLPC, Wikipedia), Becky Stern (Make), Jon Philips (Qi), Shigeru Kobayashi (Gainer), Thinh Nguyen and John Wilbanks (CC) and the sponsor of the event (littleBits, Eyebeam). Also the people from Creative Commons will be there and that is a great news as different people in the OpenHardware community had decided to use the CC licence to release the schematics and gerber files of their PCBs.

During this event, we will do a presentation of the OHANDA Trademark and the projects currently under this trademark as we will talk during the event.

Notes

[1] http://freedomdefined.org/OSHW

[2] http://www.openhardwaresummit.org

Using a LogicAnalyzer to prototype/monitor the data buses: example of the Local Expansion Bus between the CPU and the ISDN interface

In the process of developing an OpenHardware project, the prototyping process is quite important and namely the validation of the data buses exchanging telecommunications data (synchronization, reset, interrupts, tx/rx data, signaling...) between the different interfaces and chips on the hardware product.

At this step of, once the analog SP (Signal Processing) is validated, one can test the data-buses using the so-called "LogicAnalyzer" that will put the signal on the bus into readable binary data (from the TTL levels triggered on edges or any other events on the trigger line chosen). LogicAnalyzer can be quite expensive appliance (such as digital scope or frequency analyzer) but nowadays affordable device exist also allowing the hardware designer / tester to monitor the data on one bus. Such kind of LogicAnalyzer are usually based on 3 parts:

  • EZ-Hook type of connectors to probe the pins/headers on the prototype card or PCB (i.e. TP - TestPoint)
  • TTL-to-USB chip to transform the analog signal probed into binary signals
  • USB interface to connect the host-PC with the right analyzer software (usually unfortunately running for MS)

Please find a list of USB Logic Analyzer available (some supported with sigrok [1]

  • USBee SX Test Pod Logic Analyzer [2] (a HUGE sample buffer PC and USB based multifunction logic analyzer)
  • EE Electronics XLA ESLA100 (a cheap 8-channel logic analyzer)
  • ASIX Sigma (a 6 channel logic analyzer with sample rate support up to 200 MHz and with 256 Mbit on-board memory)
  • Openbench Logic Sniffer (a FPGA-based logic analyzer, supporting 32 probes for probing up to 100MHz signals)
  • Braintechnology USB-LPS (a Cypress FX2 based logic analyzer and signal generator with up to 16 channels)
  • Buspirate [3]
  • Intronix Logicport LA1034 (a FPGA-based logic analyzer, capable of sampling data on 34 channels at up to 500MHz) [4]

The one we are using for the prototyping of the XiVO OpenHardware IPBX is a Saleae Logic Analyzer with the 1.0.21 software [5]

Below are 2 snapshots of signals probed on the Local Expansion Bus connecting the CPU with the ISDN chip:

  • /CS: Chip Select signal (to indicate which chip on the LEB should be driven)
  • /RD: ReaD signal (from the CPU indicating that the data will be read from the ISDN chip registers)
  • /WR: WRite signal (from the CPU indicating that the data will be written into the ISDN chip registers)
  • ALE: Address LatchE to indicate which Address of Data to retrieve
  • D0: Bit 0 from the LEB data bus
  • D1: Bit 1 from the LEB data bus
  • D2: Bit 2 from the LEB data bus
  • A8: Address 8 (EX_ADDR8) line on the CPU used to trigger the scope or the logic analyzer

As one can see in the screenshot below, the A8 line is set on "0" + "1" which means the triggering is done on upper edge from this signal.

LEB CPU ISDN LogicAnalyzer traces

The view below is a zoomed view of the above screenshot with a focus on the triggering on A8 line

LEB CPU ISDN LogicAnalyzer traces zoom

Notes

[1] http://sigrok.org/wiki/Main_Page

[2] http://usbee.com

[3] http://dangerousprototypes.com/2009/11/03/bus-pirate-logic-analyzer-mode/

[4] http://www.pctestinstruments.com/

[5] http://www.saleae.com

The XiVO IPBX OpenHardware eco-system

As we move forward on the validation of the different functionnal block of the XiVO IPBX OpenHardware project, we can now describe more precisely the different blocks and the eco-system of the project.

The functionnal blocks are numbered now as followed for the validation and PCB Schematics :

1-CPU
2-ISDN
3-FXO-FXS
4-UART
5-EEPROM
6-ETH
7-SD-USB
8-SATA
9-LEDS
10-DDR2
11-SPI-FLASH
12-CPU-JTAG
13-PWR
14-CLK
15-RST

We will then follow-up on the documentation of the project for the validation and PCB Schematics with this numbering allowing sub-documentation and discussion for each functionnal block.

Concerning the eco-system of the project, the figure below describes the different steps to go to the production of the XiVO IPBX OpenHardware product.

XiVO IPBX OpenHardware EcoSystem

The next posts will describe the validation of the communication between the CPU1 and the ISDN2 and the FXO-FXS3.

Official OHANDA annoucement

OHANDA stands for Open Source Hardware and Design Alliance

OHANDA is an initiative to foster sustainable sharing of open hardware and design. It was first drafted at the GOSH!-Grounding Open Source Hardware summit at the Banff Centre in July 2009.

One of the first goals of the project is to build a service for sharing open hardware designs which includes a certification model and a registration. Recently we are working on getting an OpenHardwareTM off the ground.

OHANDA is work in process. The process is open ...

Please check http://www.ohanda.org and subscribe to our mailinglist: https://piksel.no/mailman/listinfo/ohanda

KiCAD: The OpenSource EDA tool for designing PCBs

This post aims at presenting KiCAD [1], THE OpenSource EDA tool for CAD file used to design PCB (Printed Circuit Boards) originally designed and written by Jean-Pierre Charras, a researcher at LIS (Laboratoire des Images et des Signaux) and a teacher at IUT de Saint Martin d'Hères (France), in the field of electrical engineering and image processing. KiCAD aims at being a tool equivalent to the "closed-non-free" CAD software like Atium Protel, Eagle, Cadence with the benefit of a free and open-source with a community of developer and early-user implementing KiCAD for industrial hardware design of PCB up to 10layers and a growing collection of component footprints and reference in the library (the standard footprints like SOTs, QFPs, BGAs are crucial to have the maximum support of the ICs, chips of the silicon manufacturers)

Kicad is a set of four softwares and a project manager:

  • Eeschema: Schematic entry.
  • Pcbnew:Board editor.
  • Gerbview: GERBER viewer (photoplotter documents).
  • Cvpcb: footprint selector for components used in the circuit design.
  • Kicad: project manager.

KiCAD early-users and developers can participate to the project on the subversion [2]

A bug tracker [3] is up and running for feedbacks from the users (GUI optimization for GNU users and Windows users mainly).

From our XiVO IPBX OpenHardware project point of view, we are also using KiCAD mainly for small PCB and Schematics of your interfaces between each functionnal block. The screen-shot below presents the KiCAD Eeschema to implement the TDM connexion between the CPU and the ISDN chip:

XiVO ISDN TDM Connexions Prototyping

The right-side toolbar is for selecting the object to include in the schematic (component, power, ground, wires ...), the top part toolbar is there for the sheet preferences and settings and for the interaction with the PCB editor and gerber exporter and viewer.

Notes

[1] http://www.lis.inpg.fr/realise_au_lis/kicad/

[2] http://kicad.svn.sourceforge.net/viewvc/kicad/

[3] https://bugs.launchpad.net/kicad

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